Method and apparatus for controlling a bias voltage of a Mach-Zehnder modulator

ABSTRACT

A method and apparatus for controlling a bias voltage of a Mach-Zehnder modulator (MZM) use a digital pilot signal and a digital correlation technique to produce a feedback signal for adjusting the bias voltage to the quadrature bias point. Embodiments of the invention include apparatuses performing a non-return-to-zero (NRZ), return-to-zero (RZ), or carrier suppressed RZ (CSRZ) high-speed optical modulation.

FIELD OF THE INVENTION

The present invention generally relates to the field of high-speedoptical communications and, more specifically, to high-speed opticalmodulators.

BACKGROUND OF THE INVENTION

In high-speed optical communications, electro-optical modulators areused to modulate a continuous wave (CW) laser output into light pulsesthat transmit voice, data, and/or video signals over fiber-optic cables.One such modulator is a Mach-Zehnder modulator (MZM). The MZM has asinusoidal transfer function of modulating voltage in relation to thelight output. To operate the MZM in a linear mode providing best opticaltransmission performance, a DC bias voltage is applied across modulatingelectrodes of the modulator. Generally, a bias point must be maintainedat the point of inflection (i.e., quadrature) of the sinusoidal transferfunction. However, the bias point is subject to a drift due to factorssuch as temperature variations, optical stress, aging of the modulator,and the like. As the bias moves away from the quadrature bias point, theMZM may cause significant intermodulation distortion in the transmittedsignal. Therefore, in operation, the bias point should be dynamicallycontrolled.

An established method for controlling the bias voltage of the MZM isbased on modulating the bias voltage with an analog (e.g., sinusoidal)pilot tone, detecting a portion of the output optical signal, anddetecting a harmonic of the pilot tone using a synchronous detector. Thedetected pilot tone is then used for generating a feedback signal thatadjusts a bias circuit such that MZM operates at a pre-selected biaspoint. However, this method provides low accuracy near the bias pointwhere the feedback signal is small and excessively sensitive to spuriousnoise components in the detected pilot tone. These drawbacks result innon-optimal value and instability of the bias voltage of the MZM.

Therefore, there is a need in the art for an improved method andapparatus for controlling a bias voltage of Mach-Zehnder modulators usedin high-speed optical communications.

SUMMARY OF THE INVENTION

The present invention is generally a method and apparatus forcontrolling a bias voltage of a Mach-Zehnder modulator (MZM) used forperforming a non-return-to-zero (NRZ), return-to-zero (RZ), or carriersuppressed RZ (CSRZ) high-speed modulation (e.g., 10–40 Gbit/s orhigher) of an optical signal.

In one embodiment of the present invention, a method for controlling thebias voltage of a MZM performing the NRZ modulation includes generatinga digital pilot signal, modulating the MZM using the digital pilotsignal, detecting a portion of an optical output signal from the MZMusing a light detector, and processing an output signal of the lightdetector using a digital correlation filter and a digital demodulator toproduce a feedback signal controlling the bias voltage of the MZM.

In another embodiment of the present invention, a method for controllingthe bias voltages of an input MZM and an output MZM coupled forperforming an RZ or CSRZ modulation includes generating a digital pilotsignal, modulating sequentially the input MZM or the output MZM usingthe digital pilot signal, detecting a portion of an optical outputsignal from the MZM using a light detector, and processing an outputsignal of the light detector using a digital correlation filter and adigital demodulator to produce a feedback signal controlling a biasvoltage of an MZM which is modulated, during at least a data samplingperiod of the processing step, using the digital pilot signal.

In still another embodiment of the present invention, an apparatus forcontrolling a bias voltage of a MZM performing an NRZ modulationincludes a generator of a digital pilot signal modulating the MZM, abias circuit generating a bias voltage for the MZM, a light detectordetecting a portion of an optical signal from the MZM, and a digitalsignal processor processing an output signal of the light detector andcoupled to a control input of the bias circuit.

In yet another embodiment of the present invention, an apparatus forcontrolling a bias voltage of an input MZM and an output MZM coupled forperforming an RZ or CSRZ modulation of an optical signal includes agenerator of a digital pilot signal for modulating the input MZM and theoutput MZM, a first bias circuit of the input MZM, a second bias circuitof the output MZM, a light detector of a portion of an optical outputsignal from the output MZM, a digital signal processor processing anoutput signal of the light detector, and a time multiplexing circuitcomprising a timing circuit controlling a first multiplexer and a secondmultiplexer, wherein the first multiplexer sequentially couples thedigital pilot signal to the input MZM or the output MZM and the secondmultiplexer couples an output of the digital signal processor to acontrol input of the bias circuit of the MZM concurrently coupled to thedigital pilot signal.

BRIEF DESCRIPTION OF THE DRAWINGS

The teachings of the present invention can be readily understood byconsidering the following detailed description in conjunction with theaccompanying drawings, in which:

FIG. 1 depicts a block diagram of an apparatus for controlling a biasvoltage of a MZM performing the NRZ modulation in accordance with oneembodiment of the present invention;

FIG. 2 depicts a block diagram of an apparatus for controlling a biasvoltage of MZMs performing the RZ or CSRZ modulation in accordance withone embodiment of the present invention;

FIG. 3 depicts an exemplary timing diagram of time multiplexing thecontrol and feedback signals in the apparatus of FIG. 2; and

FIGS. 4A–4B, together, depict a flow diagram of one embodiment of theinventive method of controlling a bias voltage of the MZM(s) performinghigh-speed modulation of an optical signal.

To facilitate understanding, identical reference numerals have beenused, where possible, to designate identical elements that are common tothe figures.

It is to be noted, however, that the appended drawings illustrate onlyexemplary embodiments of this invention and are therefore not to beconsidered limiting of its scope, for the invention may admit to otherequally effective embodiments.

DETAILED DESCRIPTION OF THE INVENTION

The present invention advantageously provides high accuracy control ofan optimal bias voltage for Mach-Zehnder modulators (MZMs) used forperforming non-return-to-zero (NRZ), return-to-zero (RZ), or carriersuppressed RZ (CSRZ) high-speed modulation (e.g., 10–40 Gbit/s orhigher) of a continuous wave (CW) optical signal. The invention employsa digital pilot tone in conjunction with a digital signal processingscheme that suppresses spurious noise components in the pilot tone andincreases signal to noise (S/N) ratio of the feedback signal controllingthe bias voltage of the MZM.

FIG. 1 depicts a block diagram of a system 100 for controlling a biasvoltage of a MZM performing the NRZ modulation in accordance with oneembodiment of the present invention. The system 100 comprises a CW laser102 (e.g., InGaAs/InP laser, and the like) coupled to a MZM 110 using apigtail 104. An optical output of the MZM 110 is coupled, using apigtail 108, to a coupler 112. The coupler 112 directs a small portionof an optical output to a photodetector (e.g., photodiode) 114, whichoutput is coupled, through an optional analog band-path filter 124 andan analog-to-digital converter ADC 126, to a digital signal processor(DSP) 140.

A digital pilot tone is produced using a digital signal generator 116.The digital signal generator 116 comprises a digital to analog converter(DAC) that converts a digital signal into an analog domain. In oneexemplary embodiment, the digital pilot tone is a digitized sinusoidalsignal (e.g., about 1 to 2 kHz) comprising at least 2 digitalcomponents. Preferably, the digitized sinusoidal signal comprises about20 or more digital components.

A controlled bias circuit 122 provides a DC bias voltage V_(B1) to theMZM 110. A nominal value of the bias voltage V_(B1) generallycorresponds to the quadrature bias point the MZM 110. In one embodiment,the digital pilot tone and the bias voltage V_(B1) are combined with anelectrical data signal 111 (e.g., 10–40 Gbit/s) using a driver 118,which output is coupled to an electrical modulating input 120 of the MZM110 (e.g., LiNbO₃ modulator, and the like electro-optic modulator). Inalternate embodiments (not shown), the driver 118 may comprise anamplifier of the data signal 111, a modulator facilitating an amplitudemodulation (AM) of the data signal 111 by the digital pilot signal, orother conventional means of coupling the data signal 111, digital pilotsignal, and bias voltage V_(B1). In yet another embodiment (also notshown), the MZM 110 and driver 118 may be integrated in a single module.

The photodiode 114 is a slow photodetector detecting the digital pilotsignal and integrating a carrier signal of the laser 102 and an opticaldata signal. In operation, an output signal of the photodiode 114generally comprises a sum of a smaller digital pilot signal embedded inlarger noise component that may further comprise strong spuriouscomponents, as well as a DC component proportional to an average opticalpower at the output of the MZM 110.

The analog band-path filter 124 has a center frequency coinciding withor close to the frequency of the digital pilot signal and a bandwidth ofabout 20%. In one embodiment (not shown), the filter 124 furthercomprises an input analog amplifier or an output analog amplifier. TheADC 126 (e.g., 12 bit ADC) transforms an analog output signal at theoutput of the filter 124 in a digital format that may be processed bythe DSP 140.

In one embodiment, the DSP 140 comprises a digital correlation filter128 and a digital synchronous demodulator 130. In alternate embodiments(not shown), at least one of the digital correlation filter 128 anddigital synchronous demodulator 130 are implemented in software (e.g.,as a software program) in a computer processor of the DSP 140, acomputer processor of the system 100, or a remote computer processor.

The digital correlation filter 128 is generally a real-timeauto-correlation filter. Such a filter operates on the basic principlethat small synchronous components (e.g., components of a digitizedsinusoidal pilot signal) can be discriminated from larger asynchronousor noise components by summing and averaging multiple data points of aninput signal (i.e., output signal of the ADC 126). In one embodiment,such data points include repetitive samples (i.e., measurements) of thedigital components of the digitized sinusoidal pilot signal. When thesummation is performed over a relatively large number of data points(e.g. at least 8 data points), asynchronous signals and noise averageout to near zero, while a small synchronous signal of interest remainsat its average level. The correlation filter 128 typically operatesunder the control of a microprocessor. Alternatively, the correlationfilter may be implemented as a software program used by the DSP 140. Anauto-correlation process generally comprises repetitive cycles eachincluding a data acquisition step and data processing (i.e., averaging)step. Such data acquisition and data processing steps may be timemultiplexed or performed simultaneously. In one embodiment, the digitalcorrelation filter 128 recovers at least one of the digital pilot signaland a first harmonic of the digital pilot signal which is(are) outputtedto the synchronous demodulator 130.

In the system 100, during a data acquisition cycle, the digitalcorrelation filter 128 samples an output signal of the ADC 126. In oneembodiment, a sampling rate of the filter 128 is about 20 kHz and thedata acquisition cycle comprises 160 data points. The data points aretemporarily stored, in a digital format, in a memory device of thecorrelation filter 128 and then are averaged. In this embodiment, at theinput of the synchronous demodulator 130, a S/N ratio of the recovered(i.e., averaged) digital pilot tone signal and the first harmonic ofsuch a signal is about 2 and, as such, 2 to 3 times greater than inconventional systems employing an analog pilot tone signal or an analogprocessing technique.

The synchronous demodulator 130 is generally a digital synchronousdetector that is inputted with an recovered output digital signal fromthe digital correlation filter 128 and the digital pilot tone signalfrom the signal generator 116. Alternatively, the synchronousdemodulator 130 may be implemented as a software program used by the DSP140. The synchronous demodulator 130 demodulates, in a conventionalmanner, the output signal from the digital correlation filter 128 andproduces a feedback signal V_(F1). The feedback signal V_(F1) comprisesthe information needed for adjusting an output voltage of the biascircuit 122 to the optimal (i.e., quadrature) bias point of the MZM 110.The feedback signal V_(F1) is applied to a control input 121 of the biascircuit 122.

In one exemplary embodiment, the DSP 140 comprises the ADC 126 mod.AD7859 available from Analog Devices, Inc. of Norwood, Mass. and thedigital correlation filter 128 that is implemented as a software programused in the processor mod. TMS320C6202 available from Texas Instruments,Inc. of Dallas, Tex.

In response to the feedback signal V_(F1), the bias circuit 122 adjuststhe output voltage V_(B1) (i.e., bias voltage) that is provided, via thedriver 118, to the MZM 110. In one embodiment, the bias circuit 122 maymaintain such adjusted value of the bias voltage for a pre-determinedtime, e.g., a duration of the cycle comprising a data acquisition stepand a data processing step of the digital correlation filter 128 or,alternatively, an integer multiple of a duration of such a cycle. In afurther embodiment (not shown) the bias circuit 122 is implemented as asoftware program within the DSP 140 and a programmable DAC thatgenerates the bias voltage.

In operation, the bias circuit 122 dynamically responds to the signalV_(F1) and maintains the bias voltage V_(B1) at the quadrature biaspoint of the MZM 110. In one illustrative embodiment, an amplitude andpolarity of the feedback signal V_(F1) define the value and polarity ofthe adjustment for the bias voltage V_(B1), respectively. In analternate embodiment (not shown), interface between the synchronousdemodulator 130 and the bias circuit 122 may be facilitated using adigital link, such as RS-232 serial interface, and the like. In afurther embodiment, the interface may be implemented, in a form of asoftware program, within the DSP 140 and/or the system 100.

In the system 100, a high S/N ratio of the recovered digital pilot tonesignal results in high accuracy of the feedback signal V_(F1)controlling the bias voltage V_(B1), as well as in immunity of thefeedback signal from the noise level and spurious noise components whichmight be present in the system.

FIG. 2 depicts a block diagram of a system 200 for controlling a biasvoltage of an input MZM and an output MZM which are coupled forperforming a RZ modulation or, alternatively, a CSRZ modulation of anoptical signal in accordance with one embodiment of the presentinvention. The system 200 comprises the CW laser 102 coupled to the MZM110 (input MZM) using a pigtail 104. The MZM 110 is optically coupled toa MZM 132 (output MZM) using a pigtail 108. An optical output of the MZM132 is coupled to the coupler 112. The coupler 112 directs a smallportion of the optical output to the photodetector 114, which output iscoupled to the DSP 140.

A modulating input 146 of the MZM 132 is electrically coupled to adriver 134 that combines an electrical data signal 133, the digitalpilot tone, and a bias voltage V_(B2) from a controlled bias circuit136. In one exemplary embodiment, the drivers 118 and 134, as well asthe bias circuits 122 and 136, may be configured and operate similarly.The data signals 111 and 133 are generally provided to the drivers 118and 134 with a phase shift φ. The phase shift φ may be controlled using,e.g., a phase-locked loop (PLL) circuit (not shown), either analog ordigital. Connections to the digital signal generator 116 and controlinputs of the bias circuits 122, 136 are administered by a timingcircuit 138 using multiplexers 142 and 144, respectively.

FIG. 3 depicts an exemplary timing diagram of time multiplexing thecontrol and feedback signals in the system 200. Specifically, a graph300 depicts a sequence of cycles 302 comprising time intervals T1 and T2and an optional time interval T3 versus time (x-axis 310). Together, aplurality of the cycles 302 represents a duration of a period 304 ofcontinuous operation of the system 200. In a further embodiment (notshown), to reduce interference between different control operations, atleast in of the time intervals T1, T2, and T3 may comprise an optionalperiod or periods of idle time.

Referring to FIG. 2, in one embodiment during a time interval T1, theoutput of the digital signal generator 116 is connected to the input ofthe driver 118 and the output of the synchronous demodulator 130 isconnected to the control input 121 of the bias circuit 122. During atime interval T2, the output of the digital signal generator 116 isconnected to the input of the driver 134 and the output of thesynchronous demodulator 130 is connected to a control input 135 of thebias circuit 136. The time intervals T1 and T2 may be separated by anoptional time interval T3. During the time interval T3, no connectionsare provided to the digital signal generator 116 and control inputs ofthe bias circuits 122, 136.

In operation, the timing circuit 138 facilitates time multiplexing ofthe connections to the digital signal generator 116, as well as tocontrol inputs of the bias circuit 122 of the MZM 110 and the biascircuit 136 of the MZM 132. A duration of the time intervals T1 and T2is selected to be an integer multiple of a duration of the cyclecomprising a data acquisition step and a data processing step in thedigital correlation filter 128.

During the time interval T1, the multiplexers 142 and 144 connect theoutput of the digital signal generator 116 to the input of the driver118 (multiplexer 142) and the output of the synchronous demodulator 130to the control input 121 of the bias circuit 122 (multiplexer 144). Inresponse, the system 200 adjusts the bias voltage V_(B1) to thequadrature bias point of the MZM 110, as discussed above in reference tothe system 100 (FIG. 1). The bias circuit 122 may maintain such anadjusted value of the bias voltage for a duration that is at least equalor greater than a sum of the time intervals T1 and T3, i.e., till theupdated feedback signal V_(F1) is provided, during the consecutive timeinterval T1 of the period 304, by the DSP 140.

During the time interval T2, the multiplexers 142 and 144 connect theoutput of the digital signal generator 116 to the input of the driver134 (multiplexer 142) and the output of the synchronous demodulator 130to the control input 135 of the bias circuit 136 (multiplexer 144).During this time interval, the DSP 140 produces a feedback signal V_(F2)that comprises the information needed for adjusting an output voltage ofthe bias circuit 136 to a pre-selected bias point (e.g., maximum,minimum, or quadrature bias point) of the MZM 132. The feedback signalV_(F2) is applied to the control input 135 of the bias circuit 136. Toproduce the feedback signals V_(F1) and V_(F2), the DSP 140 may use thesame or similar procedures and algorithms. In one exemplary embodiment,in the system 200 performing the RZ modulation, the synchronousdemodulator 130 uses the recovered digital pilot signal and the firstharmonic of the signal to produce the feedback signals V_(F2) andV_(F1), respectively.

In response to the feedback signal V_(F2), the bias circuit 136 adjuststhe bias voltage provided to the MZM 132 to the pre-selected bias point(e.g., maximum bias point) of the MZM. The bias circuit 136 may maintainsuch an adjusted value of the bias voltage for a duration that is atleast equal or greater than a sum of the time intervals T2 and T3, i.e.,till the updated feedback signal V_(F2) is provided, during theconsecutive time interval T2 of the period 304, by the DSP 140. As such,using the time multiplexing technique, the system 200 provides dynamiccontrol of the optimal bias points of the MZM 110 and MZM 132 using asingle digital pilot tone.

In the system 200, a high S/N ratio of the recovered digital pilot tonesignal results in high accuracy of the feedback signals V_(F1) andV_(F2) controlling the bias voltages V_(B1) and V_(B2), respectively,and facilitates immunity of the feedback signals from the noise leveland spurious noise components which might be present in the system.

FIGS. 4A–4B, together, depict a flow diagram of one embodiment of theinventive method for controlling a bias voltage of MZM modulators usedin high-speed optical communications as a process 400. To bestunderstand the invention, the reader should simultaneously refer toFIGS. 1–2 and 4A–4B.

The process 400 starts at step 401 and proceeds to step 402, where adigital pilot tone is generated. At step 404, the digital pilot tone isused to modulate a first MZM. At step 406, a small portion of an opticaloutput signal is detected using a slow photodetector. At step 408, anoutput signal of the photodetector is optionally filtered using aband-path filter (not shown) and then digitized using an ADC. At step410, a digital correlation filter is used to recover the digital pilottone. At step 412, a synchronous demodulator demodulates the digitalpilot tone and produces a feedback signal for a bias circuit of thefirst MZM. At step 414, the bias circuit of the first MZM adjusts thebias voltage to the quadrature bias point.

At step 416, the process 400 queries if there is another MZM (i.e.,second MZM) in the optical path. Specifically, the second MZM may bepresent in a system using the RZ or CSRZ modulation, while the systemusing the NRZ modulation generally comprises only the first MZM. If thequery of step 416 is negatively answered (shown using a link 429), theprocess 400 proceeds to step 430. If the query of step 416 isaffirmatively answered (shown using a link 417), the process 400proceeds to step 418. At step 418, the digital pilot tone is used tomodulate the second MZM. Steps 420, 422, 424, 426, and 428 are similarto the respective steps 406, 408, 410, 412, and 414, however, areperformed in reference to the second MZM.

At step 430, the process 400 queries if the optical transmission hasbeen competed. If the query of step 430 is negatively answered, theprocess 400 proceeds to step 402 to continue controlling the biasvoltage of the MZM modulators, as discussed above. If the query of step416 is affirmatively answered, the process 400 proceeds to step 432,where the process 400 ends.

While the foregoing is directed to the illustrative embodiment of thepresent invention, other and further embodiments of the invention may bedevised without departing from the basic scope thereof, and the scopethereof is determined by the claims that follow.

1. A method of controlling a bias voltage of a Mach-Zender modulator(MZM) performing a non-return-to-zero (NRZ) modulation of an opticalsignal, comprising: generating a digital pilot signal; modulating theMZM using the digital pilot signal; coupling a portion of an opticaloutput signal from the MZM to a light detector; processing an outputsignal of the light detector using a digital correlation filter torecover the digital pilot signal; and demodulating the recovered digitalpilot signal to produce a feedback signal controlling the bias voltageof the MZM.
 2. The method of claim 1 wherein the digital pilot signal isa digitized sinusoidal signal.
 3. The method of claim 1 wherein theprocessing step further comprises: filtering the output signal of thelight detector using a band-path filter digitizing the output signal ofthe light detector using an analog-to-digital converter; sampling theoutput signal of the analog-to-digital converter; and applying a digitalcorrelating technique recover at least one of the digital pilot signalor a first harmonic of the digital pilot signal.
 4. The method of claim3 wherein the digital correlating technique further comprises:time-domain averaging of a pre-determined number of samples of theoutput signal of the analog-to-digital converter.
 5. The method of claim1 wherein the demodulating step further comprises: using a digitalsynchronous demodulating technique, and generating a signal whilemaintaining a bias voltage of the MZM at a quadrature bias point.
 6. Amethod of controlling bias voltages of an input Mach-Zender modulator(MZM) and an output MZM coupled for performing a return-to-zero (RZ)modulation or a carrier suppressed RZ (CSRZ) modulation of an opticalsignal, comprising: generating a digital pilot signal; modulatingsequentially the input MZM or the output MZM using the digital pilotsignal; coupling a portion of an optical output signal from the outputMZM to a light detector; processing an output signal of the lightdetector using a digital correlation filter to recover the digital pilotsignal; and demodulating the detected digital pilot signal to produce afeedback signal controlling a bias voltage of an MZM modulated using thedigital pilot signal during at least a data sampling period of theprocessing step.
 7. The method of claim 6 wherein the digital pilotsignal is a digitized sinusoidal signal.
 8. The method of claim 6wherein the processing step further comprises: filtering the outputsignal of the light detector using a band-path filter digitizing theoutput signal of the light detector using an analog-to-digitalconverter; sampling the output signal of the analog-to-digitalconverter; and applying a digital correlating technique recover at leastone of the digital pilot signal or a first harmonic of the digital pilotsignal.
 9. The method of claim 8 wherein the digital correlatingtechnique further comprises: time-domain averaging of a pre-determinednumber of samples of the output signal of the analog-to-digitalconverter.
 10. The method of claim 6 wherein the demodulating stepfurther comprises: using a digital synchronous demodulating technique,and generating a signal while maintaining a bias voltage of the MZM at aquadrature bias point.